View 8XC196NP_293328.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
n n n n n n n n n n n n n
25 MHz Operation at 4.5-5.5 Volts 1 Mbyte of Linear Address Space Optional 4 Kbytes of ROM 1000 Bytes of Register RAM Register-register Architecture 32 I/O Port Pins 16 Prioritized Interrupt Sources 4 External Interrupt Pins and NMI Pin 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability Full-duplex Serial Port with Dedicated Baud-rate Generator Peripheral Transaction Server Event Processor Array (EPA) with 4 High-speed Capture/Compare Channels
n
n n n n n
Chip-select Unit -- 6 Chip Select Pins -- Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select -- Programmable Wait States (0, 1, 2, or 3) for Each Chip Select -- Programmable Bus Width (8- or 16bit) for Each Chip Select -- Programmable Address Range for Each Chip Select 1.12 s 16 x 16 Unsigned Multiplication 1.92 s 32/16 Unsigned Division 100-pin SQFP or 100-pin QFP Package Complete System Development Support High-speed CHMOS Technology
The 8XC196NP is a member of Intel's 16-bit MCS(R) 96 microcontroller family. The device features 1 Mbyte of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. When operating at 25 MHz in demultiplexed mode, the 8XC196NP can access a 100 ns memory device with zero wait states. The 8XC196NP is available without ROM (80C196NP) or with 4 Kbytes of ROM (83C196NP).
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. (c) INTEL CORPORATION, 1995 October 1995 Order Number: 272459-005
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
16 CPU 1000 Byte Register File 4K Bytes ROM (optional)
RALU
Interrupt Controller
24 Bytes CPU SFRs
Microcode Engine
Peripheral Transaction Server 8 16
Memory Controller with Chip Select Queue
Chip Select CS5:0#
Control Signals A19:16/ EPORT3:0
A15:0 Pulse Width Modulator
Timer 1 Timer 2
Event Processor Array
Serial Port
Baud Rate Gen
AD15:0
Port 1
Port 2
Port 3
Port 4
Port 1/ EPA3:0, Timer 1, Timer 2
Port 2/ Hold Control, SIO, EXTINT1:0
Port 3/ Port 4/ EXTINT3:2 PWM2:0
A2351-01
Figure 1. 8XC196NP Block Diagram
2
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PROCESS INFORMATION
This device is manufactured on P648, a CHMOS IV process. Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook (order number 210997). All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology.
Table 1. Thermal Characteristics Package Type 100-pin SQFP 100-pin QFP JA 55C/W 56C/W JC 14C/W 16C/W
X
Te
XX
Pa ck
8
X
Pr og
X
Pr oc
XXXXX
Pr od
XX
De
Figure 2. The 8XC196NP Family Nomenclature Table 2. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed Options no mark S SB 0 3 C 196NP no mark 25 MHz Description Commercial operating temperature range (0C to 70C) with Intel standard burn-in. QFP SQFP No ROM ROM CHMOS
mp er
vic
es
ra
uc
ag ing Op tio ns
eS
m-
sI
tF
atu re an
pe
me
nfo rm ati
am
ed
mo
ily
ry
dB ur
on
Op tio
nin Op tio ns
ns
A2815-01
3
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 3. 8XC196NP Memory Map Address (Note 1) FF FFFFH FF 3000H FF 2FFFH FF 2000H FF 1FFFH FF 0000H FE FFFFH 0F 0000H 0E FFFFH 01 0000H 00 FFFFH 00 3000H 00 2FFFH 00 2000H 00 1FFFH 00 1FE0H 00 1FDFH 00 1F00H 00 1EFFH 00 0400H 00 03FFH 00 0100H 00 00FFH 00 0018H 00 0017H 00 0000H Description External device (memory or I/O) connected to address/data bus Internal ROM or external device (memory or I/O) connected to address/data bus (determined by EA# pin) External device (memory or I/O) connected to address/data bus Overlaid memory (reserved for future devices) 896 Kbytes of external device (memory or I/O) connected to address/data bus External device (memory or I/O) connected to address/data bus External device (memory or I/O) connected to address/data bus or remapped internal ROM Memory-mapped peripheral special-function registers (SFRs) Internal peripheral special-function registers (SFRs) External device (memory or I/O) (reserved for future devices) Upper register file (general-purpose register RAM) Lower register file (general-purpose register RAM and stack pointer) Lower register file (CPU SFRs) Notes 9 2,9 3,9 3,9 9 9 5, 6,9 4, 7,9 4, 7, 10 6 8, 10 8, 11 4, 7, 8, 11
NOTES: 1. Internally, there are 24 address bits (A23:0); however, only 20 address lines (A19:0) are bonded out. The external address space is 1 Mbyte (00000-FFFFFH). 2. The 8XC196NP resets to internal address FF2080H (FF2080H in internal ROM or F2080H in external memory). 3. Do not locate code in addresses xF0000-xF00FFH. These addresses are reserved for the ICE in-circuit emulator. Unless otherwise noted, write 0FFH to reserved memory locations. 4. Unless otherwise noted, write 0 to reserved SFR bits. 5. These areas are mapped into internal ROM if the REMAP bit (CCB1.2) is set and EA# is at logic 1. Otherwise, they are mapped to external memory. 6. WARNING: The contents or functions of these memory locations may change with future device revisions, in which case a program that relies on one or more of these locations may not function properly. 7. Refer to the 8XC196NP User's Manual or 8XC196NP Quick Reference for SFR descriptions. 8. Code executed in locations 000000H to 0003FFH will be forced external. 9. Address with indirect, indexed, or extended modes. 10. Address with indirect, indexed, or extended modes or through register windows. 11. Address with direct, indirect, indexed, or extended modes.
4
RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC NC P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SB8XC196NP
View of component as mounted on PC board
Figure 3. 8XC196NP 100-pin SQFP Package
A2348-04
P3.7 / EXTINT3 P1.0 / EPA0 VCC P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1 P2.5 / HOLD# P2.6 / HLDA#
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL#
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RD# BHE# / WRH# ALE INST READY RPD ONCE VSS VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 NC VSS XTAL1 XTAL2 VSS NC P2.7 / CLKOUT
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. 8XC196NP 100-pin SQFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Name RESET# NMI EA# A0 A1 V CC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC
Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Name EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 HOLD#/P2.5 HLDA#/P2.6
Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 NC VSS
Name CLKOUT/P2.7
Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Name WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
XTAL2 XTAL1 VSS NC A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC VSS ONCE RPD READY INST ALE BHE#/WRH# RD#
NC CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 EXTINT2/P3.6
To be compatible with future versions of the Nx family, tie the no connection (NC) pins as follows: Pin 57 = VSS, Pin 16 = VCC, Pin 17 = VSS (5 volts on this pin will enable a clock doubler on future devices), and Pin 52 = VCC.
6
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 5. 100-pin SQFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 Pin 4 5 8 9 10 11 12 13 65 64 63 62 61 60 59 58 82 81 78 77 100 99 98 97 96 95 94 93 91 89 88 87 86 7 Processor Control Name CLKOUT EA# EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 Pin 51 3 46 48 25 26 2 69 1 70 55 54 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Bus Control & Status Name Pin 73 74 47 49 50 72 75 71 76 Address & Data (cont) Name AD13 AD14 AD15 Pin 85 84 83 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 18 19 20 21 23 24 27 29 30 31 82 81 78 77 46 47 48 49 50 51 25 26 41 38 39 40 45 32 33 35 37 44 NC NC NC NC No Connection Name Pin 16 17 52 57 VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 6 14 28 34 42 67 80 92 7 15 22 36 43 53 56 66 68 79 90
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC
AD0 NC RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2 NC P3.7 / EXTINT3 P1.0 / EPA0 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S8XC196NP
View of component as mounted on PC board
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL# RD# BHE# / WRH# ALE INST READY RPD ONCE VSS VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 VSS XTAL1 XTAL2 VSS P2.7 / CLKOUT NC P2.6 / HLDA# P2.5 / HOLD#
P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A2349-03
Figure 4. 8XC196NP 100-pin QFP Package
8
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. 8XC196NP 100-pin QFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD0 No Connection RESET# NMI EA# A0 A1 V CC VSS A2 A3 A4 A5 A6 A7 VCC VSS No Connection CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 Name Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name EXTINT2/P3.6 No Connection EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name HOLD#/P2.5 HLDA#/P2.6 No Connection CLKOUT/P2.7 VSS XTAL2 XTAL1 VSS A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC VSS ONCE RPD READY INST ALE BHE#/WRH# Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RD# WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 Name
9
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 7. 100-pin QFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 10 Pin 6 7 10 11 12 13 14 15 66 65 64 63 62 61 60 59 83 82 79 78 1 100 99 98 97 96 95 94 92 90 89 88 87 Processor Control Name CLKOUT EA# EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 Pin 54 5 48 50 26 28 4 70 3 71 57 56 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Bus Control & Status Name Pin 74 75 49 51 52 73 76 72 77 Address & Data (cont) Name AD13 AD14 AD15 Pin 86 85 84 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 19 20 21 22 24 25 29 31 32 33 83 82 79 78 48 49 50 51 52 54 26 28 43 40 41 42 47 34 35 37 39 46 NC NC NC NC No Connection Name Pin 2 18 27 53 VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 8 16 30 36 44 68 81 93 9 17 23 38 45 55 58 67 69 80 91
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PIN DESCRIPTIONS
Table 8. Pin Descriptions Name A15:0 Type I/O System Address Bus These address lines provide address bits 0-15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. A19:16 I/O Address Lines 16-19 These address lines provide address bits 16-19 during the entire external memory cycle, supporting extended addressing of the 1Mbyte address space. Internally, there are 24 address bits; however, only 20 address lines (A19:0) are bonded out. The external address space is 1 Mbyte (00000-FFFFFH) and the internal address space is 16 Mbytes (000000-FFFFFFH). The 8XC196NP resets to internal address FF2080H (FF2080H in internal ROM or F2080H in external memory). AD15:0 I/O Address/Data Lines The function of these pins depends on the bus size and mode. 16-bit Multiplexed Bus Mode: AD15:0 drive address bits 0-15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit Multiplexed Bus Mode: AD15:8 drive address bits 8-15 during the entire bus cycle. AD7:0 drive address bits 0-7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit Demultiplexed Mode: AD15:0 drive or receive data during the entire bus cycle. 8-bit Demultiplexed Mode: AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data that is currently on the high byte of the internal bus. ALE O Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0 for a demultiplexed bus). ALE differs from ADV# in that it does not remain active during the entire bus cycle. An external latch can use this signal to demultiplex the address bits 0-15 from the address/data bus in multiplexed mode. -- -- EPORT.3:0 Description Multiplexed with --
11
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued) Name BHE# Type O Byte High Enable The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0 selects WRH#. During 16-bit bus cycles, this active-low output signal is asserted for word reads and writes and high-byte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system data bus. Use BHE#, in conjunction with A0, to determine which memory byte is being transferred over the system bus: BHE# 0 0 1 BREQ# O A0 0 1 0 Byte(s) Accessed both bytes high byte only low byte only P2.3 Description Multiplexed with WRH#
Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. The device can assert BREQ# at the same time as or after it asserts HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is removed. You must enable the bus-hold protocol before using this signal. Clock Output Output of the internal clock generator. The CLKOUT frequency is 1/2 the internal operating frequency (FXTAL1). CLKOUT has a 50% duty cycle.
CLKOUT
O
P2.7
CS5#:0
O
Chip-select Lines 0-5 The active-low output CSx# is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x. If the external memory address is outside the range assigned to the six chip selects, no chip-select output is asserted and the bus configuration defaults to the CS5# values. Immediately following reset, CS0# is automatically assigned to the range FF2000-FF20FFH (F2000-F20FFH if external). External Access This input determines whether memory accesses to specialpurpose and program memory partitions (FF2000-FF2FFFH) are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# is not latched and can be switched dynamically during normal operating mode. Be sure to thoroughly consider the issues, such as different access times for internal and external memory, before using this dynamic switching capability. On devices with no internal nonvolatile memory, always connect EA# to VSS.
P3.5:0
EA#
I
--
12
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued) Name EPA3:0 Type I/O Description Event Processor Array (EPA) Input/Output pins These are the high-speed input/output pins for the EPA capture/compare channels. For high-speed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared output pin. EPORT.3:0 I/O Extended Addressing Port This is a 4-bit, bidirectional, memory-mapped I/O port. The pins are shared with the extended address bus A19:16. External Interrupts In normal operating mode, a rising edge on EXTINTx sets the EXTINTx interrupt pending bit. EXTINTx is sampled during phase 2 (CLKOUT high). The minimum high time is one state time. In powerdown mode, asserting the EXTINTx signal for at least 1 state time causes the device to resume normal operation. The interrupt need not be enabled, but the pin must be configured as a special-function input. If the EXTINTx interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. HLDA# O Bus Hold Acknowledge This active-low output indicates that the CPU has released the bus as the result of an external device asserting HOLD#. HOLD# I Bus Hold Request An external device uses this active-low input signal to request control of the bus. This pin functions as HOLD# only if the pin is configured for its special function and the bus-hold protocol is enabled. Setting bit 7 of the window selection register enables the bus-hold protocol. INST O Instruction Fetch This active-high output signal is valid only during external memory bus cycles. When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches. NMI I Nonmaskable Interrupt In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than one state time to guarantee that it is recognized. -- -- P2.5 P2.6 A19:16 Multiplexed with P1.3:0
EXTINT0 EXTINT1 EXTINT2 EXTINT3
I
P2.2 P2.4 P3.6 P3.7
13
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued) Name ONCE Type I On-circuit Emulation Holding ONCE high during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. This mode puts all pins into a high-impedance state, thereby isolating the device from other components in the system. The value of ONCE is latched when the RESET# pin goes inactive. While the device is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent accidental entry into ONCE mode, connect the ONCE pin to VSS. P1.3:0 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.5:0 P3.6 P3.7 P4.2:0 P4.3 PWM2:0 I/O Port 1 This is a standard, bidirectional port that is multiplexed with individually selectable special-function signals. EPA3:0 T1CLK T1DIR T2CLK T2DIR TXD RXD EXTINT0 BREQ# EXTINT1 HOLD# HLDA# CLKOUT CS5:0# EXTINT2 EXTINT3 PWM2:0 Description Multiplexed with --
I/O
Port 2 This is a standard, bidirectional port that is multiplexed with individually selectable special-function signals.
I/O
Port 3 This is an 8-bit, bidirectional, standard I/O port. Port 4 This is a 4-bit, bidirectional, standard I/O port with high-current drive capability. Pulse Width Modulator Outputs These are PWM output pins with high-current drive capability. The duty cycle and frequency-pulse-widths are programmable.
I/O
O
P4.2:0
RD#
O
Read Read-signal output to external memory. RD# is asserted only during external memory reads. Ready Input This active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally. When READY is high, CPU operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers, Register 0, or the chip-select x bus control register. READY is ignored for all internal memory accesses.
--
READY
I
--
14
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued) Name RESET# Type I/O Reset A level-sensitive reset input to and open-drain system reset output from the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown, standby, and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode. After a device reset, the first instruction fetch is from FF2080H (or F2080H in external memory). For the 80C196NP, the program and special-purpose memory locations (FF2000-FF2FFFH) reside in external memory. For the 83C196NP, these locations can reside either in external memory or in internal ROM. RPD I Return from Powerdown Timing pin for the return-from-powerdown circuit. If your application uses powerdown mode, connect a capacitor between RPD and VSS if the internal oscillator is the clock source. The capacitor causes a delay that enables the oscillator to stabilize before the internal CPU and peripheral clocks are enabled. The capacitor is not required if your application uses powerdown mode and if an external clock input is the clock source. If your application does not use powerdown mode, leave this pin unconnected. RXD I/O Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. T1CLK I Timer 1 External Clock External clock for timer 1. Timer 1 increments (or decrements) on both rising and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature counting mode. and External clock for the serial I/O baud-rate generator input (program selectable). T2CLK I Timer 2 External Clock External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. Also used in conjunction with T2DIR for quadrature counting mode. T1DIR I Timer 1 External Direction External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and decrements when it is low. Also used in conjunction with T1CLK for quadrature counting mode. T2DIR I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. Also used in conjunction with T2CLK for quadrature counting mode. 15 P1.7 P1.5 P1.6 P1.4 P2.1 -- Description Multiplexed with --
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued) Name TXD Type O Description Transmit Serial Data In serial I/O modes 1, 2, and 3, TXD is used to transmit serial port data. In mode 0, it is used as the serial clock output. Digital Supply Voltage Connect each VCC pin to the digital supply voltage. VSS GND Digital Circuit Ground Connect each VSS pin to ground through the lowest possible impedance path. WR# O Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0 selects WRL#. WRH# O Write High During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0 selects WRH#. WRL# O Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes. During 8-bit bus cycles, WRL# is asserted for all write operations. The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0 selects WRL#. XTAL1 I Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1. XTAL2 O Inverted Output for the Crystal/Resonator Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator. -- -- WR# BHE# WRL# -- Multiplexed with P2.0
VCC
PWR
--
ELECTRICAL CHARACTERISTICS
16
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This document contains information on
Storage Temperature .................................. -60C to +150C products in the design phase of development. The Supply Voltage with Respect to VSS .............. -0.5 V to +7.0 V specifications are subject to change without notice. Power Dissipation .......................................................... 1.5 W Do not finalize a design with this information.
Revised information will be published when the product is available. Verify with your local Intel TA (Ambient Temperature Under Bias)................ 0C to +70C sales office that you have the latest datasheet VCC (Digital Supply Voltage) ............................. 4.5 V to 5.5 V before finalizing a design. OPERATING CONDITIONS*
FXTAL1 (Input frequency for VCC = 4.5-5.5 V) (Note 1) ................................................. 8 MHz to 25 MHz
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These NOTES: are stress ratings only. Operation beyond the "Operating 1. This device is static and should operate below 1 Hz, but Conditions" is not recommended and extended exposure has been tested only down to 8 MHz. beyond the "Operating Conditions" may affect device reliability.
17
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
DC Characteristics
Table 9. DC Characteristics at VCC = 4.5 - 5.5 V (Note 1) Symbol ICC Parameter VCC Supply Current Min Ty p 80 Max 120 Units mA Test Conditions XTAL1 = 25 MHz VCC = 5.5 V Device in Reset XTAL1 = 25 MHz VCC = 5.5 V VCC = 5.5 V VSS < VIN < VCC
IIDLE IPD ILI VIL VIH VIL1 VIH1 VOL
Idle Mode Current Powerdown Mode Current (Note 2) Input Leakage Current (all input pins except RESET) Input Low Voltage (all pins) Input High Voltage Input Low Voltage XTAL1 Input High Voltage XTAL1 Output Low Voltage (output configured as complementary) (Note 3,6) Output High Voltage (output configured as complementary) (Note 6) Output Low Voltage on P4.x (output configured as complementary) VCC - 0.3 VCC - 0.7 VCC - 1.5 -0.5 0.2 VCC +1 -0.5 0.7 VCC
24 50
36 75 10 0.8 VCC + 0.5 0.3 VCC VCC + 0.5 0.3 0.45 1.5
mA A A V V V V V V V V V V
IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA IOL = 10 mA IOL = 15 mA
VOH
VOL1
0.45 0.6
V V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For temperatures below 100C, typical is 10 A. 3. For all pins except P4.3:0, which have higher drive capability (see VOL1). 4. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). 5. Pin capacitance is not tested. CS is based on design simulations. 6. During normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: Group P1 P2 P3 P4 EPORT Individual P1, P2, P3 P4 18 10 18 10 10 IOL(mA) 42 42 42 45 21 IOH(mA) 42 42 42 21 21
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 9. DC Characteristics at VCC = 4.5 - 5.5 V (Note 1) (Continued) Symbol VOL2 VOH1 VOL3 VOL4 Parameter Output Low Voltage in RESET on ALE, INST, and NMI Output High Voltage in RESET (Note 4) Output Low Voltage in RESET for ONCE pin Output Low Voltage on XTAL2 VCC - 0.7 0.45 0.3 0.45 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5 0.3 10 9 95 Min Ty p Max 0.45 Units V V V V V V V V V V pF k VCC = 5.5 V, VIN = 4.0 V Test Conditions IOL = 3 A IOH = -3 A IOL = 30 A IOL = 100 A IOL = 700 A IOL = 3 mA IOH = -100 A IOH = -700 A IOH = -3 mA
VOH2
Output High Voltage on XTAL2
VTH+ -VTH- CS RRST
Hysteresis voltage width on RESET# pin Pin Capacitance (any pin to VSS) (Note 5) RESET Pull-up Resistor
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For temperatures below 100C, typical is 10 A. 3. For all pins except P4.3:0, which have higher drive capability (see VOL1). 4. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). 5. Pin capacitance is not tested. CS is based on design simulations. 6. During normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: Group P1 P2 P3 P4 EPORT Individual P1, P2, P3 P4 10 18 10 10 IOL(mA) 42 42 42 45 21 IOH(mA) 42 42 42 21 21
19
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
ICC, IIDLE vs. Frequency 100 90 80
ICC, IIDLE (mA)
IIDLE@VCC = 5.0 V ICC@VCC = 5.0 V
70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Frequency (MHz)
A3080-01
Figure 5. ICC, IIDLE versus Frequency
20
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
AC Characteristics -- Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 10. AC Characteristics, Multiplexed Bus Mode Symbol Parameter VCC = 4.5 V - 5.5 V Min Max Units
The 8XC196NP Will Meet These Specifications FXTAL1 TXTAL1 TXHCH TCLCL TCHCL TAVRL TAVWL TWHSH TRHSH TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH Input frequency on XTAL1 Period, 1/FXTAL1 XTAL1 High to CLKOUT High/Low CLKOUT Cycle Time CLKOUT High Period AD15:0 Valid to RD# Low AD15:0 Valid to WR# Low A19:16, CSx# Hold after WR# Rising Edge A19:16, CSx# Hold after RD# Rising Edge CLKOUT Low to ALE High ALE Low to CLKOUT High ALE Cycle Time ALE High Period AD15:0 Valid to ALE Low AD15:0 Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# Low Period RD# High to ALE High RD# Low to Address Float ALE Low to WR# Low CLKOUT Low to WR# Low Data Valid before WR# High CLKOUT High to WR# High WR# Low Period TXTAL1 - 15 -15 TXTAL1 - 15 -10 TXTAL1 - 5 10 10 8 40 10 2TXTAL1 TXTAL1 - 10 2TXTAL1 - 20 2TXTAL1 - 10 0 0 -10 -15 4TXTAL1 TXTAL1 - 10 TXTAL1 -15 TXTAL1 - 25 TXTAL1 - 15 0 TXTAL1 TXTAL1 - 5 TXTAL1 + 15 5 20 TXTAL1 + 10 10 10 ns ns ns (2) ns ns ns ns ns ns (2) ns (3) ns ns ns ns (2) ns ns (2) TXTAL1 + 10 25 125 110 MHz ns ns ns ns ns ns
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only.
21
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 10. AC Characteristics, Multiplexed Bus Mode (Continued) Symbol Parameter VCC = 4.5 V - 5.5 V Min Max Units
The 8XC196NP Will Meet These Specifications TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High AD15:8 Hold after WR# High BHE#, INST Hold after RD# High AD15:8 Hold after RD# High TXTAL1 - 20 TXTAL1 - 12 TXTAL1 - 10 TXTAL1 - 10 TXTAL1 - 10 TXTAL1 - 10 TXTAL1 + 20 ns ns (3) ns ns (4) ns ns (4)
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only.
Table 11. AC Characteristics, Multiplexed Bus Mode Symbol Parameter VCC = 4.5 V - 5.5 V Min Max Units
The External Memory System Must Meet These Specifications TAVYV TYLYH TCLYX TAVDV TRLDV TSLDV TCLDV TRHDZ TRXDX AD15:0 Valid to READY Setup Non READY Time READY Hold after CLKOUT Low AD15:0 Valid to Input Data Valid RD# Active to Input Data Valid Chip-select Low, A19:16 Valid to Data Valid CLKOUT Low to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive 0 2TXTAL1 - 50 No Upper Limit 0 TXTAL1 - 10 3TXTAL1 - 40 TXTAL1 - 20 4TXTAL1 - 50 TXTAL1 - 35 TXTAL1 - 5 ns ns ns ns ns ns (1) ns (2) ns (2)
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states.
22
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
SYSTEM BUS TIMINGS, MULTIPLEXED BUS
TXTAL1
XTAL1
TCLCL TXHCH TCHCL
CLKOUT
TRLCL TCLLH TLLCH TLHLH
ALE
TLHLL TLLRL TRLRH TRHLH
RD#
TAVLL TLLAX TRLAZ TRLDV TRHDZ
AD15:0 (read)
Address Out TAVDV TLLWL TWLWH
Data
TWHLH
WR#
TQVWH TWHQX
AD15:0 (write)
Address Out
Data Out TRHBX TWHBX
Address Out
BHE#, INST
Valid TRHAX TWHAX
AD15:8
TSLDV
Address Out
A19:16 CSx#
Address Out TWHSH TRHSH
A2844-01
Figure 6. System Bus Timing Diagram (Multiplexed Bus Mode) 23
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
READY TIMING, MULTIPLEXED BUS
TCLYX (max) CLKOUT TAVYV READY TLHLH + 2TXTAL1 ALE TRLRH + 2TXTAL1 RD# TRLDV + 2TXTAL1 TAVDV + 2TXTAL1 AD15:0 (read) WR# TQVWH + 2TXTAL1 AD15:0 (write) BHE#, INST A19:16 CSx#
Address Out Valid Extended Address Out Valid
T0016-02
TCLYX (min)
Address Out
Data In
TWLWH + 2TXTAL1
Data Out
Figure 7. READY Timing Diagram (Multiplexed Bus Mode)
24
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
AC Characteristics -- Demultiplexed Bus Mode
Test Coditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 12. AC Characteristics, Demultiplexed Bus Mode Symbol Parameter VCC = 4.5 V - 5.5 V Min Max Units
The 8XC196NP Will Meet These Specifications FXTAL1 TXTAL1 TXHCH TCLCL TCHCL TAVRL TAVWL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCH TRLRH TRHLH TRLAZ TLLWL TWLCH TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX Input frequency on XTAL1 Period, 1/FXTAL1 XTAL1 High to CLKOUT High/Low CLKOUT Cycle Time CLKOUT High Period A19:0, CSx# Valid to RD# Low A19:0, CSx# Valid to WR# Low CLKOUT Low to ALE High ALE Low to CLKOUT High ALE Cycle Time ALE High Period Address Valid to ALE Low Address Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT High RD# Low Period RD# High to ALE High RD# Low to Address Float ALE Low to WR# Low WR# Low to CLKOUT High Data Valid before WR# High CLKOUT High to WR# High WR# Low Period Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High NA -5 3TXTAL1 - 37 - 15 2TXTAL1 - 10 TXTAL1 - 20 TXTAL1 - 5 TXTAL1 - 10 TXTAL1 + 20 5 10 8 40 10 2TXTAL1 TXTAL1 - 10 2TXTAL1 - 30 2TXTAL1 - 25 - 10 - 15 4TXTAL1 TXTAL1 - 10 NA NA NA 0 2TXTAL1 - 10 TXTAL1 - 5 TXTAL1 + 20 NA 15 TXTAL1 + 10 10 10 TXTAL1 + 10 25 125 110 MHz ns ns ns ns ns ns ns ns ns (2) ns ns ns ns ns ns (2) ns (3) ns ns ns ns (2) ns ns (2) ns ns (3) ns
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 25
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 12. AC Characteristics, Demultiplexed Bus Mode (Continued) Symbol Parameter VCC = 4.5 V - 5.5 V Min Max Units
The 8XC196NP Will Meet These Specifications TWHAX TRHBX TRHAX A19:0, CSx# Hold after WR# High BHE#, INST Hold after RD# High A19:0, CSx# Hold after RD# High 0 TXTAL1 - 10 0 ns ns ns
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states. 3. Assuming back-to-back bus cycles.
Table 13. AC Characteristics, Demultiplexed Bus Mode Symbol Parameter VCC = 4.5 V - 5.5 V Min Max Units
The External Memory System Must Meet These Specifications TAVYV TYLYH TCLYX TAVDV TRLDV TCLDV TRHDZ TRXDX A19:0, CSx# Valid to READY Setup Non READY Time READY Hold after CLKOUT Low A19:0, CSx# Valid to Input Data Valid RD# Active to Input Data Valid CLKOUT Low to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive 0 3TXTAL1 - 60 No Upper Limit 0 TXTAL1 - 10 4TXTAL1 - 50 2TXTAL1 - 25 TXTAL1 - 35 TXTAL1 - 5 ns ns ns (1) ns (2) ns (2) ns ns ns
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states.
26
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
SYSTEM BUS TIMINGS, DEMULTIPLEXED BUS
TXTAL1
XTAL1
TCLCL TXHCH TCHCL
CLKOUT
TCLDV TLHLH
TCLLH
TLLCH
ALE
TLHLL TRLCH TRLRH TRHLH
RD#
TRLDV TRHDZ
AD15:0 (read)
TAVDV TWLWH TWLCH TQVWH
Valid TCHWH TWHLH
WR#
TWHQX
AD15:0 (write)
Valid TRHBX TWHBX
BHE#, INST
Valid
TRHAX
TWHAX Address
A19:0 CSx#
Address Out
A2845-01
Figure 8. System Bus Timing Diagram (Demultiplexed Bus Mode)
27
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
READY TIMING, DEMULTIPLEXED BUS
TCLYX (max) CLKOUT TAVYV READY TLHLH + 2TXTAL1 ALE TRLRH + 2TXTAL1 RD# TRLDV + 2TXTAL1 TAVDV + 2TXTAL1 AD15:0 (read) TWLWH + 2TXTAL1 WR# TQVWH + 2TXTAL1 AD15:0 (write) BHE#, INST A19:0 CSx#
Data Out Valid Extended Address Out Data
TCLYX (min)
Valid
T0015-02
Figure 9. READY Timing Diagram (Demultiplexed Bus Mode)
28
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
HOLD#/HLDA# Timing
Table 14. HOLD#/HLDA# Timings Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV HOLD# Setup Time CLKOUT Low to HLDA# Low CLKOUT Low to BREQ# Low HLDA# Low to Address Float HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven CLKOUT Low to HLDA# High CLKOUT Low to BREQ# High HLDA# High to Address No Longer Float HLDA# High to BHE#, INST, RD#, WR# Valid -25 -25 -20 -20 Parameter V CC = 4.5 V - 5.5 V Min 65 -15 -15 15 15 33 25 15 25 Max Units ns (1) ns ns ns ns ns ns ns ns
NOTE: 1. To guarantee recognition at next clock.
CLKOUT
THVCH
HOLD#
THVCH
Hold Latency
TCLHAL
HLDA#
TCLHAH
TCLBRL
BREQ#
TCLBRH
THALAZ
A19:0, AD15:0 CSx#, BHE#, INST, RD#, WR# WRL#, WRH# ALE
THAHAX THAHBV
Weakly held inactive
THALBZ
TCLLH
Start of strongly driven ALE
A2460-03
Figure 10. HOLD#/HLDA# Timing Diagram 29
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
AC Characteristics -- Serial Port, Shift Register Mode
Table 15. Serial Port Timing -- Shift Register Mode Symbol TXLXL Parameter Serial Port Clock period (SP_BAUD x002H) (SP_BAUD = x001H) (Note 1) Output data setup to clock high Output data hold after clock high Next output data valid after clock high Input data setup to clock high Input data hold after clock high Last clock high to output float 2TXTAL1 + 200 0 5TXTAL1 VCC = 4.5 V - 5.5 V Min 6TXTAL1 4TXTAL1 3TXTAL1 2TXTAL1 - 50 2TXTAL1 + 50 Max Units
ns ns ns ns ns ns ns ns
TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ
NOTE: 1. The minimum baud-rate register (SP_BAUD) value for receive is x002H and the minimum baud-rate register value for transmit is x001H.
TXLXL TXD TQVXH RXD (Out) 0 TDVXH RXD (In) Valid Valid Valid 1 2 3 TXHDX Valid Valid Valid Valid Valid 4
TXLXH
TXHQV TXHQX 5 6 TXHQZ 7
A2080-02
Figure 11. Serial Port Waveform -- Shift Register Mode
30
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
External Clock Drive
Table 16. External Clock Drive Symbol 1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Input frequency Period (TXTAL1) High Time Low Time Rise Time Fall Time Min 8 40 0.35TXTAL1 0.35TXTAL1 Max 25 125 0.65TXTAL1 0.65TXTAL1 10 10 Units MHz ns ns ns ns ns
TXHXX 0.7 VCC + 0.5 V
TXLXH 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V T
XLXL
TXHXL
T
XLXX
0.3 VCC - 0.5 V
A2119-02
Figure 12. External Clock Drive Waveforms
3.5 V
2.0 V 0.8 V
Test Points
2.0 V 0.8 V
0.45 V
AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A2120-02
Figure 13. AC Testing Output Waveforms During 5.0 Volt Testing
31
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-01
Figure 14. Float Waveforms During 5.0 Volt Testing
EXPLANATION OF AC SYMBOLS
Each AC timing symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
H -- High L -- Low V -- Valid X -- No Longer Valid Z -- Floating
Signals:
A -- Address AD -- Address/Data Bus for Multiplexed Bus Mode B -- BHE# C -- CLKOUT D -- DATA G -- Buswidth H -- HOLD# HA -- HLDA# L -- ALE/ADV# BR -- BREQ# R -- RD# W -- WR#/WRH#/WRL# X -- XTAL1 Y -- READY Q -- Data Out S -- Chip Select
32
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
8XC196NP ERRATA
Change identifiers have been used on embedded products since 1990. The change identifier is the last character in the FPO number. The FPO number is typically a nine character number located on the second line of the topside package mark. The following errata listing is applicable to the B-step (denoted by a "B" or "C" at the end of the topside tracking number): 1. Any jump, conditional jump, or call instruction located within six bytes of the top of a page, i.e., 0FFFA-0FFFFH, may cause a jump to the wrong page. To ensure this problem does not occur, place at least six NOPs at the top of each page.
4.
(1-Mbyte mode only.) If a standard interrupt occurs at approximately the same time (this time is code dependent and therefore cannot be stated as an exact number of state times) as a PTS serviced interrupt, the PTS interrupt may be processed as a standard interrupt. The standard interrupt service routine for a PTS serviced interrupt (End-of-PTS) is typically used to modify the PTS control block and reenable the PTS by setting the corresponding bit in the PTSSEL register. When this anomaly occurs, the End-of-PTS service routine will execute regardless of the value in PTSCOUNT. As a result, an undetermined number of PTS cycles will not occur. This applies to all PTS interrupts.
The following errata listing is applicable to the A- step (denoted by an "A" at the end of the topside tracking number): 1. Any jump, conditional jump, or call instruction located within six bytes of the top of a page, i.e., 0FFFA-0FFFFH, may cause a jump to the wrong page. To ensure this problem does not occur, place at least six NOPs at the top of each page. The illegal opcode interrupt vector is not taken when an illegal opcode is encountered. A branch to an unknown location occurs. (1-Mbyte mode only.) If an interrupt is aborted, intentionally or unintentionally, an undesired branch to the lowest priority interrupt vector (FF2000H) may occur even if the lowest priority interrupt is not enabled. This may occur if any bit in the INT_MASK, INT_MASK1, INT_PEND, or INT_PEND1 register is cleared after the corresponding INT_PEND or INT_PEND1 bit is set.
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a "B" at the end of the topside tracking number. Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. The following are important changes to the 272459005 datasheet: 1. 2. 3. 4. Revised Tables 8 through 15 and Figures 5, 6, 7, and 13 to reflect new or changed information. Added Table 3 and Figure 9. The input frequency on XTAL1, formerly called FOSC, is now denoted by FXTAL1. The AC characteristics tables have been divided into the following: the timing specifications met by the device, and the timing specifications that must be met by the external memory system. Maximum IOL and IOH specifications added to the DC characteristics tables. AC timings TAVWL and TAVRL added to the AC characteristics-multiplexed bus mode tables.
2.
3.
5. 6.
33
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
34
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
35
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
36
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
37
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
38
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
39
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
40
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
41
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
42
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
43
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
44
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
45
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
46
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
47
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
48
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
49
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
50
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
51

▲Up To Search▲

Price & Availability of 8XC196NP

	To Download 8XC196NP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .